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? semiconductor components industries, llc, 2009 december, 2009 ? rev. p0 1 publication order number: NCP1379/d NCP1379 product preview quasi-resonant current-mode controller for high-power universal off-line supplies the NCP1379 hosts a high ? performance circuitry aimed to powering quasi ? resonant converters. capitalizing on a proprietary valley ? lockout system, the controller shifts gears and reduces the switching frequency as the power loading becomes lighter. this results in a stable operation despite switching events always occurring in the drain ? source valley. this system works down to the 4 th valley and toggles to a variable frequency mode beyond, ensuring an excellent standby power performance. the controller includes an over power protection circuit which clamps the delivered power at high ? line. safety ? wise, a fixed internal timer relies on the feedback voltage to detect a fault. once the timer elapses, the controller stops and enters auto ? recovery mode, ensuring a low duty ? cycle burst operation. to further improve the safety of the power supply, the NCP1379 features a pin to implement a combined brown ? out/overvoltage protection. particularly well suited for tvs power supply applications, the controller features a low startup voltage allowing the use of an auxiliary power supply to power the device. features ? quasi ? resonant peak current ? mode control operation ? valley switching operation with valley ? lockout for noise ? immune operation ? frequency foldback at light load to improve the light load efficiency ? adjustable over power protection ? auto ? recovery output short ? circuit protection ? fixed internal 80 ms timer for short ? circuit protection ? combined overvoltage protection and brown ? out ? +500 ma / ? 800 ma peak current source/sink capability ? internal temperature shutdown ? direct optocoupler connection ? low v cc(on) allowing to use a standby power supply to power the device ? extremely low no ? load standby power ? so8 package ? these devices are pb ? free and are rohs compliant typical applications ? high power ac ? dc converters for tvs, set ? top boxes etc. ? offline adapters for notebooks this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. http://onsemi.com see detailed ordering and shipping information in the package dimensions section on p age 21 of this data sheet. ordering information 1 8 1379 alyw 1 8 1379 = specific device code a = assembly location l = wafer lot y = year w = work week = pb ? free package marking diagrams soic ? 8 d suffix case 751 1 2 3 4 8 7 6 5 pin connections zcd fb cs gnd ct fault vcc drv quasi ? resonant pwm controller for high power ac ? dc wall adapters
NCP1379 http://onsemi.com 2 typical application example vout hv ? bulk gnd gnd NCP1379 zcd / opp 1 2 8 6 7 vcc . . . figure 1. typical application schematic 5 3 4 pin function description pin n pin name function pin description 1 zcd zero crossing detection adjust the over power protection connected to the auxiliary winding, this pin detects the core reset event. also, injecting a negative voltage smaller than 0.3 v on this pin will perform over power protection. 2 fb feedback pin hooking an optocoupler collector to this pin will allow regulation. 3 cs current sense this pin monitors the primary peak. 4 gnd ? the controller ground 5 drv driver output the driver?s output to an external mosfet 6 v cc supplies the controller this pin is connected to an external auxiliary voltage. 7 fault overvoltage protection brown ? out this pin observes the hv rail and protects the circuit in case of low main conditions. it also offers a way to latch the circuit in case of over voltage event. 8 c t timing capacitor a capacitor connected to this pin acts as the timing capacitor in fold- back mode.
NCP1379 http://onsemi.com 3 internal circuit architecture fb ct ict + ? + ? zc d la ux 10 v esd vth drv de ma g s r q q / 4 vcc vdd vdd vcc v cc management latch vdd rpullup fa ul t drv ga te gr a nd reset gr a nd reset gr a nd reset drv clamp ipflag pw mreset ovp/bo gn d up down timer reset v ccstop hv + ? ibo noise delay vbo bo r e se t + ? vclamp vovp noi s e de l a y bo r e se t logic block vdd rclamp vdd cs rsense leb 1 + ? soft-start soft-start end ? then 1 else 0 ipflag + ? ss end pw mreset opp v ilimit i peak(vco) = 17.5 % v ilimit leb 2 + ? v cs(stop ) cs s top le b 2 is shorter than le b 1 css top v cc aux 5 s time out 40 s time out ss end the 40 s time out is active only during s oft ? start ss end figure 2. internal circuit architecture 3 s blanking c t s e tpoint ct discharge r s q q
NCP1379 http://onsemi.com 4 maximum ratings table(s) symbol rating value unit v cc(max) i cc(max) maximum power supply voltage, vcc pin, continuous voltage maximum current for vcc pin ? 0.3 to 28 30 v ma v drv(max) i drv(max) maximum driver pin voltage, drv pin, continuous voltage maximum current for drv pin ? 0.3 to 20 1000 v ma v max i max maximum voltage on low power pins (except pins drv and v cc ) current range for low power pins (except pins zcd, drv and v cc ) ? 0.3 to 10 10 v ma i zcd(max) maximum current for zcd pin +3 / ? 2 ma r ja thermal resistance junction ? to ? air 120 c/w t j(max) maximum junction temperature 150 c operating temperature range ? 40 to +125 c storage temperature range ? 60 to +150 c esd capability, human body model (hbm) model (note 1) 4 kv esd capability, cdm model (note 1) 2 kv stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device series contains esd protection and exceeds the following tests: human body model 4000 v per mil ? std ? 883, method 3015. charged device model 2000 v per jedec standard jesd22 ? c101d 2. this device contains latchup protection and exceeds 100 ma per jedec standard jesd78. electrical characteristics (unless otherwise noted: for typical values t j = 25 c, v cc = 12 v, v zcd = 0 v, v fb = 3 v, v cs = 0 v, v fault = 1.5 v, c t = 680 pf) for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 12 v) symbol parameter conditions min typ max unit supply section ? startup and supply circuits v cc(on) v cc(off) v cc(hyst) v cc(reset) supply voltage startup threshold minimum operating voltage hysteresis v cc(on) ? v cc(off) internal logic reset v cc increasing v cc decreasing v cc decreasing 10.5 8.3 2.0 6 11.4 9.0 2.4 7 12.3 9.4 ? 8 v t vcc(off) v cc(off) noise filter ? 5 ? s t vcc(reset) v cc(reset) noise filter ? 20 ? s i cc(start) startup current fb pin open v cc = v cc(on) ? 0.5 v ? 0.7 1.2 ma i cc1 i cc2 i cc3a i cc3b supply current device disabled/fault (note 3) device enabled/no output load on pin 5 device switching (f sw = 65 khz) device switching (f sw around 12 khz) v cc > v cc(off) f sw = 10 khz c drv = 1 nf, f sw = 65 khz c drv = 1 nf, v fb = 1.25 v ? ? ? ? 1.7 1.7 2.65 2.0 2.0 2.0 3.00 ? ma current comparator ? current sense v ilim current sense voltage threshold v fb = 4 v, v cs increasing 0.76 0.80 0.84 v t leb leading edge blanking duration for v ilim minimum on time minus t ilim 210 275 330 ns i bias input bias current (note 3) drv high ? 2 ? 2 a t ilim propagation delay v cs > v ilim to drv turn ? off ? 125 175 ns i peak(vco) percentage of maximum peak current level at which vco takes over (note 4) v fb = 0.4 v, v cs increasing 15.4 17.5 19.6 % 3. guaranteed by design 4. the peak current setpoint goes down as the load decreases. it is frozen below i peak(vco) (i peak = cst) 5. if negative voltage in excess to ? 300 mv is applied to zcd pin, the current setpoint decrease is no longer guaranteed to be linear 6. minimum value for t j = 125 c
NCP1379 http://onsemi.com 5 electrical characteristics (unless otherwise noted: for typical values t j = 25 c, v cc = 12 v, v zcd = 0 v, v fb = 3 v, v cs = 0 v, v fault = 1.5 v, c t = 680 pf) for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 12 v) symbol unit max typ min conditions parameter current comparator ? current sense v opp(max) setpoint decrease for v zcd = ? 300 mv (note 5) v zcd = ? 300 mv, v fb = 4 v, v cs increasing 35.0 37.5 40.0 % v cs(stop) threshold for immediate fault protection activation 1.125 1.200 1.275 v t bcs leading edge blanking duration for v cs(stop) ? 120 ? ns drive output ? gate drive r snk r src drive resistance drv sink drv source v drv = 10 v v drv = 2 v ? ? 12.5 20 ? ? i snk i src drive current capability drv sink drv source v drv = 10 v v drv = 2 v ? ? 800 500 ? ? ma t r rise time (10 % to 90 %) c drv = 1 nf, v drv from 0 to 12 v ? 40 75 ns t f fall time (90 % to 10 %) c drv = 1 nf, v drv from 0 to 12 v ? 25 60 ns v drv(low) drv low voltage v cc = v cc(off) + 0.2 v c drv = 1 nf, r drv =33 k 8.4 9.1 ? v v drv(high) drv high voltage (note 6) v cc = v cc(max) c drv = 1 nf 10.5 13.0 15.5 v demagnetization input ? zero voltage detection circuit v zcd(th) zcd threshold voltage v zcd decreasing 35 55 90 mv v zcd(hys) zcd hysteresis v zcd increasing 15 35 55 mv v ch v cl input clamp voltage high state low state i pin1 = 3.0 ma i pin1 = ? 2.0 ma 8 ? 0.9 10 ? 0.7 12 ? 0.3 v t dem propagation delay v zcd decreasing from 4 v to ? 0.3 v ? 150 250 ns c par internal input capacitance ? 10 ? pf t blank blanking delay after on ? time 2.30 3.15 4.00 s t outss t out timeout after last demag transition during soft ? start after the end of soft ? start 28 5.0 41 5.9 54 6.7 s r zcd(pdown) pulldown resistor (note 3) 140 320 500 k timing capacitor ? timing capacitor v ct(max) maximum voltage on c t pin v fb < v fb(th) 5.15 5.40 5.65 v i ct source current v ct = 0 v 18 20 22 a v ct(min) minimum voltage on c t pin, discharge switch activated ? ? 90 mv c t recommended timing capacitor value 220 pf feedback section ? feedback r fb(pullup) internal pullup resistor 15 18 22 k i ratio pin fb to current setpoint division ratio 3.8 4.0 4.2 v fb(th) fb pin threshold under which c t is clamped to v ct(max) 0.26 0.30 0.34 v 3. guaranteed by design 4. the peak current setpoint goes down as the load decreases. it is frozen below i peak(vco) (i peak = cst) 5. if negative voltage in excess to ? 300 mv is applied to zcd pin, the current setpoint decrease is no longer guaranteed to be linear 6. minimum value for t j = 125 c
NCP1379 http://onsemi.com 6 electrical characteristics (unless otherwise noted: for typical values t j = 25 c, v cc = 12 v, v zcd = 0 v, v fb = 3 v, v cs = 0 v, v fault = 1.5 v, c t = 680 pf) for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 12 v) symbol unit max typ min conditions parameter feedback section ? feedback v h2d v h3d v h4d v hvcod v hvcoi v h4i v h3i v h2i valley threshold fb voltage where 1 st valley ends and 2 nd valley starts fb voltage where 2 nd valley ends and 3 rd valley starts fb voltage where 3 rd valley ends and 4 th valley starts fb voltage where 4 th valley ends and vco starts fb voltage where vco ends and 4 th valley starts fb voltage where 4 th valley ends and 3 rd valley starts fb voltage where 3 rd valley ends and 2 nd valley starts fb voltage where 2 nd valley ends and 1 st valley starts v fb decreases v fb decreases v fb decreases v fb decreases v fb increases v fb increases v fb increases v fb increases 1.316 1.128 0.846 0.732 1.316 1.504 1.692 1.880 1.4 1.2 0.9 0.8 1.4 1.6 1.8 2.0 1.484 1.272 0.954 0.828 1.484 1.696 1.908 2.120 v protections ? fault protection t shdn thermal shutdown device switching (f sw around 65 khz) 140 ? 170 c t shdn(hys) thermal shutdown hysteresis ? 40 ? c t ovld overload timer v fb = 4 v, v cs > v ilim 75 85 95 ms t ovld(off) off phase in auto ? recovery fault mode 1.0 1.2 1.4 s t sstart soft ? start duration v fb = 4 v, v cs ramping up, measured from 1 st drv pulse to v cs(peak) = 90% of v ilim 2.8 3.8 4.8 ms v bo brown ? out level v fault decreasing 0.744 0.800 0.856 v i bo sourced hysteresis current v fault > v bo v fault = v bo + 0.2 v 9 10 11 a t bo(delay) delay before entering and exiting brown ? out 22.5 30.0 37.5 s v ovp internal fault detection level for ovp v fault increasing 2.35 2.5 2.65 v t latch(delay) delay before latch confirmation (ovp) 22.5 30 37.5 s v fault(clamp) clamped voltage (fault pin left open) fault pin open 1.0 1.2 1.4 v r fault(clamp) clamping resistor (note 3) 1.30 1.55 1.80 k 3. guaranteed by design 4. the peak current setpoint goes down as the load decreases. it is frozen below i peak(vco) (i peak = cst) 5. if negative voltage in excess to ? 300 mv is applied to zcd pin, the current setpoint decrease is no longer guaranteed to be linear 6. minimum value for t j = 125 c
NCP1379 http://onsemi.com 7 11.10 11.15 11.20 11.25 11.30 11.35 11.40 ? 40 ? 20 0 20 40 60 80 100 120 figure 3. v cc(on) vs. junction temperature t j , junction temperature ( c) v cc(on) , (v) 8.80 8.82 8.84 8.86 8.88 8.90 8.92 8.94 8.96 ? 40 ? 20 0 20 40 60 80 100 120 figure 4. v cc(off) vs. junction temperature t j , junction temperature ( c) v cc(off) , (v) 1.3 1.4 1.5 1.6 1.7 1.8 1.9 ? 40 ? 20 0 20 40 60 80 100 120 figure 5. i cc2 vs. junction temperature t j , junction temperature ( c) i cc2 , (ma) 2.3 2.4 2.5 2.6 2.7 2.8 2.9 ? 40 ? 20 0 20 40 60 80 100 120 figure 6. i cc3a vs. junction temperature i cc3a , (ma) t j , junction temperature ( c) ? 40 ? 20 0 20 40 60 80 100 120 t j , junction temperature ( c) i cc3b , (ma) 2.6 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 figure 7. i cc3b vs. junction temperature 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 ? 40 ? 20 0 20 40 60 80 100 120 t j , junction temperature ( c) figure 8. i cc(start) vs. junction temperature i cc(start) , ( a)
NCP1379 http://onsemi.com 8 790 792 794 796 798 800 802 804 806 808 810 ? 40 ? 20 0 20 40 60 80 100 120 figure 9. v ilim vs. junction temperature t j , junction temperature ( c) v ilim , (mv) 230 240 250 260 270 280 290 ? 40 ? 20 0 20 40 60 80 100 120 figure 10. t leb vs. junction temperature t j , junction temperature ( c) t leb , (ns) 1.18 1.19 1.20 1.21 1.22 1.23 1.24 ? 40 ? 20 0 20 40 60 80 100 120 figure 11. v cs(stop) vs. junction temperature t j , junction temperature ( c) v cs(stop) , (v) 36.40 36.60 36.80 37.00 37.20 37.40 37.60 37.80 38.00 ? 40 ? 20 0 20 40 60 80 100 120 t j , junction temperature ( c) figure 12. v opp(max) vs. junction temperature v opp(max) , (%) 8.8 8.9 9.0 9.1 9.2 9.3 9.4 ? 40 ? 20 0 20 40 60 80 100 120 figure 13. v drv(low) vs. junction temperature v drv(low) , (v) t j , junction temperature ( c) 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 ? 40 ? 20 0 20 40 60 80 100 120 t j , junction temperature ( c) figure 14. v drv(high) vs. junction temperature v drv(high) , (v)
NCP1379 http://onsemi.com 9 30.0 40.0 50.0 60.0 70.0 80.0 90.0 ? 40 ? 20 0 20 40 60 80 100 120 v zcd(th) , (v) t j , junction temperature ( c) figure 15. v zcd(th) vs. junction temperature 15.0 20.0 25.0 30.0 35.0 40.0 45.0 50.0 ? 40 ? 20 0 20 40 60 80 100 120 t j , junction temperature ( c) figure 16. v zcd(hys) vs. junction temperature v zcd(hys) , (v) 3.00 3.05 3.10 3.15 3.20 3.25 3.30 ? 40 ? 20 0 20 40 60 80 100 120 figure 17. t blank vs. junction temperature t j , junction temperature ( c) t blank , ( s) 38 39 40 41 42 43 44 45 46 ? 40 ? 20 0 20 40 60 80 100 120 t j , junction temperature ( c) figure 18. t outss vs. junction temperature t outss , ( s) 5.2 5.4 5.6 5.8 6.0 6.2 6.4 ? 40 ? 20 0 20 40 60 80 100 120 figure 19. t out vs. junction temperature t j , junction temperature ( c) t out , ( s) 780 785 790 795 800 805 810 ? 40 ? 20 0 20 40 60 80 100 120 t j , junction temperature ( c) figure 20. v bo vs. junction temperature v bo , (mv)
NCP1379 http://onsemi.com 10 9.2 9.4 9.6 9.8 10.0 10.2 10.4 ? 40 ? 20 0 20 40 60 80 100 120 figure 21. i bo vs. junction temperature i bo , ( a) t j , junction temperature ( c) application information NCP1379 implements a standard current ? mode architecture operating in quasi ? resonant mode. thanks to a proprietary circuitry, the controller prevents valley ? jumping instability and steadily locks out in selected valley as the power demand goes down. once the fourth valley is reached, the controller continues to reduce the frequency further down, offering excellent efficiency over a wide operating range. due to a fault timer combined to an opp circuitry, the controller is able to efficiently limit the output power at high ? line. ? quasi ? resonance current ? mode operation: implementing quasi ? resonance operation in peak current ? mode control, the NCP1379 optimizes the efficiency by switching in the valley of the mosfet drain ? source voltage. due to a proprietary circuitry, the controller locks ? out in a selected valley and remains locked until the output loading significantly changes. this behavior is obtained by monitoring the feedback voltage. when the load becomes lighter, the feedback setpoint changes and the controller jumps into the next valley. it can go down to the 4 th valley if necessary. beyond this point, the controller reduces its switching frequency by freezing the peak current setpoint. during quasi ? resonance operation, in case of very damped valleys, a 5.9 s timer adds the missing valleys. ? frequency reduction in light ? load conditions: when the 4 th valley is left, the controller reduces the switching frequency which naturally improves the standby power by a reduction of all switching losses. ? overpower protection (opp): when the voltage on zcd pin swings in flyback polarity, a direct image of the input voltage is applied on zcd pin. we can thus reduce the peak current depending of the zcd pin voltage level during the on ? time. ? internal soft ? start: a soft ? start precludes the main power switch from being stressed upon start ? up. its duration is fixed and equal to 3.8 ms. ? fault input: the NCP1379 and d versions include a brown ? out circuit which safely stops the controller in case the input voltage is too low. restart occurs via a complete startup sequence (latch reset and soft ? start). during normal operation, the voltage on this pin is clamped to 1.2 v to give enough room for ovp detection. if the voltage on this pin increases above 2.5 v, the part latches ? off. ? short ? circuit protection: short ? circuit and especially over ? load protections are difficult to implement when a strong leakage inductance between auxiliary and power windings affects the transformer (where the auxiliary winding level does not properly collapse in presence of an output short). here, when the internal 0.8 v maximum peak current limit is activated, the timer starts counting up. if the fault disappears, the timer counts down. if the timer reaches completion while the error flag is still present, the controller stops the pulses and goes into auto ? recovery mode.
NCP1379 http://onsemi.com 11 NCP1379 operating modes NCP1379 has two operating mode: quasi ? resonant operation and vco operation for the frequency foldback. the operating mode is fixed by the fb voltage as portrayed by figure 22: ? quasi ? resonant operation occurs for fb voltage higher than 0.8 v (fb decreasing) or higher than 1.4 v (fb increasing) which correspond to high output power and medium output power. the peak current is variable and is set by the fb voltage divided by 4. ? frequency foldback or vco mode occurs for fb voltage lower than 0.8 v (fb decreasing) or lower than 1.4 v (fb increasing). this corresponds to low output power. ? during vco mode, the peak current decreases down to 17.5% of its maximum value and is then frozen. the switching frequency is variable and decreases as the output load decreases. ? the switching frequency is set by the end of charge of the capacitor connected to the c t pin. this capacitor is charged with a constant current source and the capacitor voltage is compared to an internal threshold fixed by fb voltage. when this capacitor voltage reaches the threshold the capacitor is rapidly discharged down to 0 v and a new period start. figure 22. operating valley according to fb voltage valley detection and selection the valley detection is done by monitoring the voltage of the auxiliary winding of the transformer. a valley is detected when the voltage on pin 1 crosses down the 55 mv internal threshold. when a valley is detected, an internal counter is incremented. the operating valley (1 st , 2 nd , 3 rd or 4 th ) is determined by the fb voltage as shown by figure 22.
NCP1379 http://onsemi.com 12 fb ct ict + ? + ? zcd la ux 10 v esd vth drv 3 us puls e de m a g s r q q leakage blanking vdd vdd ct discharge rpullup drv logic block vdd tim e out cs comparator ct setpoint v fbth v fb figure 23. valley detection circuit as the output load decreases (fb voltage decreases the valleys are incremented from the first to the fourth. when the fourth valley is reached, if fb voltage further decreases below 0.8 v, the controller enters vco mode. during vco operation, the peak current continues to decrease until it reaches 17.5% of the maximum peak current: the switching frequency expands to deliver the necessary output power. this allows achieving very low standby power consumption. the figure 24 shows a simulation case where the output current of a 19 v / 60 w decreases from 2.8 a to 0.1 a. no instability is seen during the valley transitions (figures 25, 26, 27 and 28)
NCP1379 http://onsemi.com 13 figure 24. output load is decreased from 2.4 a to 0.5 a at 120 vdc input voltage
NCP1379 http://onsemi.com 14 figure 25. zoom 1: 1 st to 2 nd valley transition figure 26. zoom 2: 2 nd to 3 rd valley transition
NCP1379 http://onsemi.com 15 figure 27. zoom 3: 3 rd to 4 th valley transition figure 28. zoom 4: 4 th valley to vco mode transition time out in case of extremely damped free oscillations, the zcd comparator can be unable to detect the valleys. to avoid such situation, NCP1379 integrates a time out function that acts as a substitute clock for the decimal counter inside the logic bloc. the controller thus continues its normal operation. to avoid having a too big step in frequency, the time out duration is set to 5.9 s. figures 30 and 31 detail the time out operation. the NCP1379 also features an extended time out during the soft ? start. indeed, at startup, the output voltage reflected on the auxiliary winding is low. because of the voltage drop introduced by the over power compensation diode (figure 35), the voltage on the zcd pin is very low and the zcd comparator might be unable to detect the valleys. in this condition, setting the drv latch with the 5.9 s time ? out leads to a continuous conduction mode operation (ccm) at the beginning of the soft ? start. this ccm operation only last a few cycles until the voltage on zcd pin becomes high enough to be detected by the zcd comparator. to avoid this, the time ? out duration is extended to 40 s during the soft ? start in order to ensure that the transformer is fully demagnetized before the mosfet is turned ? on.
NCP1379 http://onsemi.com 16 + ? zc d 10 v es d vth drv 3 us pulse + ? 5. 9 us ti m e ? out 100 ns de ma g leakage blanking vdd logi c block vdd ti meout + ? 40 us ti m e ? out 100 ns vdd ss end ss e nd figure 29. time out circuit figure 30. time out case n 1: the 3 rd valley is missing
NCP1379 http://onsemi.com 17 figure 31. time out case n 2: the 3 rd and 4 th valley are missing vco mode vco operation occurs for fb voltage lower than 0.8 v (fb decreasing), or lower than 1.4 v (fb increasing). this corresponds to low output power. during vco operation, the switching frequency is variable and expands as the output power decreases. the peak current is fixed to 17.5% of his maximum value when v fb < 0.56 v. the frequency is set by the end of charge of the capacitor connected to the c t pin. this capacitor is charged with a constant current source and its voltage is compared to an internal threshold (v fbth ) fixed by fb voltage (see figure 23). when this capacitor voltage reaches the threshold, the capacitor is rapidly discharged down to 0 v and a new period start. the internal threshold is inversely proportional to fb voltage. the relationship between v fb and v fbth is given by equation 1. v fbth 6.5 (10 3)v fb (eq. 1) when v fb is lower than 0.3 v, v ct is clamped to v ct(max) which is typically 5.5 v. figure 32 shows the vco mode at works . figure 32. in vco mode, as the power output decreases the frequency expands
NCP1379 http://onsemi.com 18 short ? circuit or overload mode figure 33 shows the implementation of the fault timer. zcd/opp laux s r q q cs rsense leb1 + ? soft ? start vcc au x v cc management latch vdd fau l t grand reset grand reset drv soft ? s t art end ? t hen 1 else 0 ipflag + ? ss en d pw mr eset up down timer reset vccstop fb/4 opp v il im it + ? leb2 v cs(stop) csstop csstop vccstop figure 33. fault detection schematic when the current in the mosfet is higher than v ilim /r sense , ?max ip? comparator trips and the digital timer starts counting: the timer count is incremented each 10 ms. when the current comes back within safe limits, ?max ip? comparator becomes silent and the timer count down: the timer count is decremented each 10 ms. in normal overload conditions the timer reaches its completion when it has counted up 8 times 10 ms. when the timers reaches its completion, the circuit enter auto ? recovery mode: the circuit stops all operations during 1.2 s typically and re ? start. this ensures a low duty ? cycle burst operation in fault mode (around 6.7%). in parallel to the cycle ? by ? cycle sensing of the cs pin, another comparator with a reduced leb (t bcs ) and a threshold of 1.2 v is able to sense winding short ? circuit and immediately stop the controller. this additional protection is also auto ? recovery.
NCP1379 http://onsemi.com 19 figure 34. auto ? recovery overload protection chronograms over power compensation the over power compensation is achieved by monitoring the signal on zcd pin (pin 1). indeed, a negative voltage applied on this pin directly affects the internal voltage reference setting the maximum peak current (figure 35). when the power mosfet is turned ? on, the auxiliary winding voltage becomes a negative voltage proportional to the input voltage. as the auxiliary winding is already connected to zcd pin for the valley detection, by selecting the right values for r opu and r opl , we can easily perform over power compensation. zcd/opp esd pr ot ect ion au x ropu ropl 1 rz cd cs + ? vth drv tblank leakage blanking demag opp v il imit ipflag figure 35. over power compensation circuit to ensure optimal zero ? crossing detection, a diode is needed to bypass r opu during the off ? time. if we apply the resistor divider law on pin 1 during the on ? time, we obtain the following relationship:
NCP1379 http://onsemi.com 20 r zcd r opu r opl ? n p,aux v in v opp v opp (eq. 2) where: n p,aux is the auxiliary to primary turn ration: n p,aux = n aux / n p v in is the dc input voltage v opp is the negative opp voltage by selecting a value for r opl , we can easily deduce r opu using equation 2. while selecting the value for r opl , we must be careful not choosing a too low value for this resistor in order to have enough voltage for zero ? crossing detection during the off ? time. we recommend having at least 8 v on zcd pin, the maximum voltage being 10 v. during the off ? time, zcd pin voltage can be expressed as follows: v zcd r opl r zcd ropl v auz v d (eq. 3) we can thus deduce the relationship between r opl and r zcd : r zcd r opl v aux v d v zcd v zcd (eq. 4) design example: ? v aux = 18 v ? v d = 0.6 v ? n p,aux = 0.18 if we want at least 8 v on zcd pin, we have: r zcd r opl v aux v d v zcd v zcd 18 0.6 8 8 1.2 (eq. 5) we can choose: r zcd = 1 k and r opl = 1 k . for the over power compensation, we ne ed to decrease the peak current by 37.5% at high line (370 vdc). the corresponding opp voltage is: v opp 0.375 v ilim ? 300 mv (eq. 6) using equation 2, we have: r zcd r opu r opl ? n p,aux v in v opp v opp (eq. 7) ? 0.18 370 ( ? 0.3 ) ( ? 0.3 ) 221 thus, r opu 221 ropl r zcd 221 1k 1k 220 k (eq. 8) overvoltage protection / brown ? out NCP1379 combine brown ? out and overvoltage detection on the pin fault. s r q q vcc s r q q grand reset drv ovp/bo hv ? bulk + ? ibo noi s e de l a y vbo bo reset + ? vclamp vovp noi s e de l a y rc l a mp cs c omp rbou rbol dz vdd la tc h clamp 7 figure 36. brown ? out and overvoltage protection in order to protect the power supply against low input voltage condition, the pin 7 permanently monitors a fraction of the bulk voltage through a voltage divider. when this image of bulk voltage is below the v bo threshold, the controller stops switching. when the bulk voltage comes back within safe limits, the circuit restarts pulsing. the hysteresis for the brown ? out function is implemented with a high side current source sinking 10 a when the brown ? out comparator is high (v bulk > v bulk(on) ) in order to avoid having a too high voltage on pin 7 if the bulk voltage is high, an internal clamp limits the voltage. in case of over voltage, the zener diode will start to conduct and inject current inside the internal clamp resistor r clamp thus causing pin 7 voltage to increase. when this voltage reaches v ovp , the controller latches ? off and stays latched. the controller will be reset if v cc falls bellow v cc(reset) or if a brown ? out occurs (figure 37).
NCP1379 http://onsemi.com 21 figure 37. operating chronograms in case of overvoltage with NCP1379 supplied by an auxiliary power supply the following equations show how to calculate the brown ? out resistors. first of all, select the bulk voltage value at which the controller must start switching (v bulk(on) ) and the bulk voltage for shutdown (v bulk(off) ). then use the following equation to calculate r bou and r bol . r bol v bo v bulk(on) v bulk(off) i bo v bulk(on) v bo (eq. 9) r bou r bol v bulk(on) v bo v bo (eq. 10) design example v bo = 0.8 v i bo = 10 a we select: v bulk(on) = 120 v, v bulk(off) = 60 v r bol v bo v bulk(on) v bulk(off) i bo v bulk(on) v bo (eq. 11) 0.8 ( 120 60 ) 10x10 ? 6 ( 120 0.8 ) 40.3 k r bou r bol v bulk(on) v bo v bo (eq. 12) 40.3x10 3 ( 120 0.8 ) 0.8 6m ordering information device package type shipping ? NCP1379dr2g soic ? 8 (pb free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NCP1379 http://onsemi.com 22 package dimensions soic ? 8 nb case 751 ? 07 issue aj seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NCP1379/d the products described herein (NCP1379), may be covered by one or more of the following u.s. patents; 6,362,067 and 5,073,850. there may be other patents pending. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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